An often used method for transmitting data in a data transmission network is to pack (multiplex) the information together with other information from other data sources and transmit data in the form of packets over a transmission channel. This means that the transmission medium is used in a more effective way and that the transmission costs are reduced. In general, data is transmitted through the network at higher clock rates as compared to the clock rate of the original data source. When the information is received it is required that the original clock information is regenerated.
A common method for achieving this is to store data intermediately in a FIFO (First In First out) memory. Out of this memory, data may then be read at a rate which corresponds to the original rate. An oscillator of the VCO type (voltage Controlled Oscillator) or the VCXO type (Voltage Controlled X-tal (Crystal) Oscillator) is often used for generating clock pulses for the read-out. The control voltage of the oscillator will then be proportional to the content level of the FIFO memory, i.e. the larger amount of data in the FIFO memory, the higher read-out rate.
Some common problems associated with this device is to obtain sufficiently jitter-free clock pulses with a reasonable depth of the FIFO, and that the information regarding the content level in most cases is not available in standard FIFO components. Another problem which arises when the transmission channel transmits a data packet into the FIFO is that the content level momentarily increases and leads to a quick increase of the read-out rate. Thereafter, no data arrives at the FIFO during a period, whereby the clock rate decreases until another data packet arrives, and so on. This is repeated periodically and leads to variations in the rate of the read-out clock (jitter).
In order to counteract this, it is common to increase the depth of the FIFO memory and to filter the control signal. The drawback with this is that the solution becomes more complex (deeper FIFO) and, because of the fact that the control signal is more heavily filtered, that the oscillators (VCXO/VCO) will experience difficulties in following the natural rate variations which may occur in the data signal.
The FIFO's which are available on the market today are often provided with "flags" which denote the content level of the memory, typically 1/2, 3/4 and 1/4. These flags may be utilized when regenerating the clock rate, but in order to get this regenerating to work satisfactorily there is required a considerably higher resolution, which implies adding external circuits.
Several devices are known which utilize the flags of the FIFOs'. In U.S. Pat. No. 5,007,070, the flags are utilized so that when the content level of the FIFO is greater than 3/4, the read-out rate is increased until the content level decreases to below the 1/2 value. In a corresponding way the rate is decreased if the content level becomes less that 1/4 until the content level exceeds the 1/2 value. When the content level is between 1/4 and 3/4, the rate is not changed.
In the device according to U.S. Pat. No. 4,270,183, the content level of the FIFO is controlled, and by means of a 1/2 value a counter is "synchronized", which counter controls the total content level in the FIFO. The value of the counter controls a rate-supplying VCO via a digital/analog converter.
Use of these known devices in a packet data network is however unsuitable since these devices also suffer from the drawback that if the data amount which has been read varies heavily, for example through the fact that data is received in the form of packets, the amount of data in the form of the number of bits in the FIFO will instantaneously increase heavily. Due to the fact that the known methods measure the data amount more or less continously in the FIFO, and thereby control the read-out clock, the control signal to the read-out clock will instantaneously increase heavily, even though there is an attempt to filter it to a certain limit.
The object of the present invention is thus to eliminate the above-mentioned problems by means of a method and a device for regenerating a clock rate which generates clock pulses for the read-out of data which to the greatest possible extent is free from jitter and which is not instantaneously affected by data sets which vary in packet data networks in the memory which is utilized for inter-mediate data storage.